(1) Field of the Invention
This invention relates to digital information processing, particularly as such information is processed for transmission and/or recording such as in magnetic tape recorders. In particular, it relates to systems and methods for providing digital signals which are self-clocking and which facilitates serially encoding information into frames while minimizing bandwidth requirements.
(2) Description of the Prior Art
With the advent of digital data communication, transmission and recording systems, a number of schemes for encoding data in digital form have been developed. While early codes were not self-clocking, and therefore required a separate clock or synchronization channel to ensure reliable decoding, more recent and widely used codes such as non-return to zero mark (NRZ-M) have been developed in which a clock or bit sync signal is built into the data code to enable self-clocking and the elimination of a separate sync or clock track.
In NRZ-M recording, a transition is provided only when a digital one occurs, and no transitions are provided when digital zeros occur. Thus, a series of "1"s or "0"s will essentially result in a shift in the DC level. Because such a code has no way to define a unit or bit cell, it is not self-clocking, and clock information must be added on separate tracks, with an attendant waste of record medium or transmission equipment, as well as limiting the ultimate density of recording due to potential skew errors. Nevertheless, NRZ recording is the workhorse of the recording industry due to the efficient bandwidth requirements and ready implementation.
Because random sequences of "1"s and "0"s can result in pulse sequences having long equivalent wavelengths, other codes, such as phase modulation (PM) have been developed. In PM codes, the bandwidth is reduced to one octave by providing an output for each bit, whether it be a one or zero, thus also making the code self-clocking. Since in PM codes, for example, a "0" may be represented as a positive transition at the center of the bit cell, a succession of either "1"s or "0"s may be seen to generate a frequency f.sub.o =1/c, where c is the duration of a unit or bit cell. Analogously, a succession of 1-0-1-0 bits may be seen to generate a frequency of f.sub.o /2, i.e., a frequency having a period equal to twice the cell duration. The possible generation of two characteristic frequencies has resulted in this code sometimes being identified as 2F code.
In order to avoid problems with the detection of the polarity of transitions, the Miller code, otherwise known as the delay modulation (DM), modified frequency modulation (MFM) or 3F code has also been developed. See U.S. Pat. No. 3,108,261 (Miller). In that code format, "1"s are represented as transitions at a particular location of the respective bit cells, such as at the center of bit cells, regardless of the polarity, and "0"s are represented as the absence of a transition at the particular location of a cell, and the insertion of a transition at the beginning of a cell if the preceding cell is also a zero. Thus, in that system, a succession of "1"s or "0"s will give rise to a first frequency f.sub.1 =1/2c. Similarly, it may be readily appreciated that a succession of 1-0-1-0 digits results in the generation of a second frequency f.sub.2 =f.sub.1 /2=1/4c, while a succession of 1-0- 0-1-0-0-1 digits results in the generation of a third frequency f.sub.3 =2f.sub.1 /3=1/3c.
The three frequencies possible of being generated thus give rise to the 3F nomenclature. The primary virtue of the Miller code is that while the bandwidth of the code is essentially the same as that of the NRZ code, self-tracking capability is added, albeit at the expense of a need to generate a 1/2 bit cell time, hence a 2f clock, and the inability to recover requisite phase information in order to properly decode the signal back to NRZ upon playback until a 1-0-1 sequence is received.
In addition to such systems for establishing bit sync or self-clocking capabilities, it is also desirable to utilize formats in which incoming data is partitioned into blocks or frames of data such that error checking code words, parity and the like may be inserted. Such schemes likewise require the addition of a unique succession of bits as a frame sync word to delineate each frame. Prior art frame sync codes generally require storage systems in which entire frames are delayed in temporary memories upon playback and frame synchronizer circuits "look" at the entire frame to determine the presence of a particular alternating pattern (see U.S. Pat. No. 4,002,845). In other frame synchronizer systems, a long pulse such as provided in Miller Code by a succession of "0"s has also been suggested, but is undesirable in that it adds a significant DC component which greatly expands the bandwidth requirements. Similarly, a high frequency, such as four or more multiples of a basic clock rate may also be employed, again at the expense of system complexity and greater bandwidth.